Power optimization of binary division based on FPGA

In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be challenge to design high performance low-power systems. Therefore, designers are trying reduce dissipation these systems by using optimization techniques. Different mathematical operations can found the architectures most The focus this paper is division. comparison other basic computational operations, division requires more iterations, takes long time, covers area, consumes from system. result, system's speed divider order improve its overall performance. This focuses on dynamic dissipation. determine which lowest power, different system designs digit-recurrence algorithms, such as restoring non-restoring suggested. An innovative power-optimization technique, hardware descriptions language (VHDL) utilized suggested designs. VHDL technique achieved higher at 93.66% for with internal-loop iteration, than traditional approaches.